This invention relates to monolithic integrated circuit devices, their structure, and preparation, and more particularly to their fabrication using ion implantation techniques.
The progress in solid state technology is largely determined by the ability to control and modify material parameters in a well defined manner. Semiconductors are a typical example, where minute traces of impurities will markedly influence the electrical properties. The concept of introducing dopants into semiconductors by means of high energetic particles is well known. This introduction of particles is commonly referred to as ion implantation which is defined as a process in which a beam of energetic particles is directed against a body of materials to selectively affect electrical and/or chemical changes in the body by the causing of the ions, of the beam, to pass into the body of the treated material.
Ion implantation of impurities into semiconductor substrates has a number of significant advantages in the fabrication of semiconductor devices over the more conventional introduction by thermal diffusion. Since ion implantation is not a high temperature process, a larger number of materials, including organic photoresists, can be used as masking for controlling the area of implantation into the substrate. Also, multiple impurity introduction operations can be achieved without resort to high temperatures. Exposure to high temperatures, as in thermal diffusion, disperses the impurities previously introduced. Ion implantation techniques permit greater control of the placement and depth of penetration into the semiconductor. In general, the total amounts of impurities introduced and the depths of penetration can be more closely controlled by ion implantation techniques than with thermal diffusion.
Consequently, integrated circuit devices can be made smaller, with greater precision, with better control of heating, and with higher operating speeds using ion implantation technology. As the semiconductor devices become smaller, parasitic capacitances associated with metallurgy and passivation layers becomes more significant. While parasitic capacitances cannot be eliminated, it is important that they be made as uniform and predictable as possible in order that their effects can be accommodated in the best possible manner. A significant parasitic capacitance variation is associated with the metallurgy of a device and is particularly concerned with the thickness of the dielectric layer which separates the metallurgy from the semiconductor substrate and the active areas therein. In ordinary semiconductor processing, windows are formed for introducing impurities, both for ion implantation and thermal diffusion techniques. Following the introduction of the impurities into the semiconductor substrate, the surface of the substrate, normally silicon, is reoxidized. Since the silicon for this thermal oxidation operation is derived from the substrate, the interface between the oxide and the substrate is depressed. This effect combined with inherent differences in the oxide thicknesses, compared to the oxide left in place which is thicker than the re-oxidized areas produces significant surface dielectric layer thickness differences. In the parasitic capacitor, the metallurgy consists of one capacitor plate, the silicon substrate the other plate, and the passivating surface oxide layer acts as the dielectric. The thickness of the dielectric thus significantly influences the parasitic capacitance. When the thickness varies the parasitic capacitance becomes quite unpredictable.